The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Feb. 15, 2016
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Jixin Yu, Milpitas, CA (US);

Yanli Zhang, San Jose, CA (US);

Zhenyu Lu, Milpitas, CA (US);

Johann Alsmeier, San Jose, CA (US);

Daxin Mao, Cupertino, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 29/423 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/535 (2013.01); H01L 27/11556 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01);
Abstract

A method of manufacturing a structure includes forming an in-process alternating stack including insulating layers and spacer material layers over a substrate, forming two sets of stepped surfaces by dividing the in-process alternating stack into a first alternating stack and a second alternating stack, the first alternating stack having first stepped surfaces and the second alternating stack having second stepped surfaces, forming at least one memory stack structure through the first alternating stack, each of the at least one memory stack structure including charge storage regions, a tunneling dielectric, and a semiconductor channel, replacing portions of the insulating layers in the first alternating stack with electrically conductive layers while leaving intact portions of the insulating layers in the second alternating stack, and forming a contact via structure through the second alternating stack to contact a peripheral semiconductor device under the second stack.


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