The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Nov. 20, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Rung-Yuan Lee, New Taipei, TW;

Yu-Ting Li, Chiayi, TW;

Jing-Yin Jhang, Tainan, TW;

Chen-Yi Weng, New Taipei, TW;

Jia-Feng Fang, Changhua County, TW;

Yi-Wei Chen, Taichung, TW;

Wei-Jen Wu, Tainan, TW;

Po-Cheng Huang, Kaohsiung, TW;

Fu-Shou Tsai, Keelung, TW;

Kun-Ju Li, Tainan, TW;

Wen-Chin Lin, Tainan, TW;

Chih-Chien Liu, Taipei, TW;

Chih-Hsun Lin, Ping-Tung County, TW;

Chun-Yuan Wu, Yun-Lin County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/306 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30625 (2013.01); H01L 21/28123 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.


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