The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

May. 26, 2015
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventors:

Genta Mizuno, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Jayavel Pachamuthu, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); H01L 27/1157 (2017.01); H01L 29/792 (2006.01); H01L 27/11565 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/7923 (2013.01);
Abstract

A memory cell can be formed with a pair of charge storage regions. The pair of charge storage regions can be two portions of a charge storage region that are located at the same level and are positioned adjacent to two different control gate electrodes. Alternately, the pair of charge storage regions can be two disjoined structures located on opposite sides of a portion of a semiconductor channel. Yet alternately, the pair of charge storage regions can be two disjoined structures located at the same level, and on two laterally split semiconductor channel. The memory cell can be employed to store two bits of information within the pair of charge storage regions located at the same level within a vertical memory string that employs a single memory opening.


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