The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Mar. 21, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peter Baars, Dresden, DE;

Juergen Faul, Radebeul, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/11541 (2017.01); H01L 27/11521 (2017.01); H01L 27/11536 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11541 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0886 (2013.01); H01L 27/11521 (2013.01); H01L 27/11536 (2013.01); H01L 29/42328 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/788 (2013.01);
Abstract

A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.


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