The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Jul. 12, 2013
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Vijay Parthasarathy, Sunnyvale, CA (US);

Sujit Banerjee, San Jose, CA (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66659 (2013.01); H01L 21/2652 (2013.01); H01L 21/26586 (2013.01); H01L 29/0634 (2013.01); H01L 29/7835 (2013.01); H01L 29/402 (2013.01); H01L 29/42368 (2013.01);
Abstract

A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.


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