The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

May. 23, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Yi Lu, Singapore, SG;

Purakh Raj Verma, Singapore, SG;

Dongli Wang, Singapore, SG;

Deyan Chen, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/761 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 21/26513 (2013.01); H01L 21/761 (2013.01); H01L 29/0653 (2013.01);
Abstract

Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure.


Find Patent Forward Citations

Lu, Yi. (2017). Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same (U.S. Patent No. 9660020). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9660020

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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