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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9659869 B1

PDFFull Text
Date of Patent:
May. 23, 2017

Filed:

Sep. 28, 2012

Forming barrier walls, capping, or alloys /compounds within metal lines

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher J Jezewski, Hillsboro, OR (US);

Alan M Meyers, Beaverton, OR (US);

Kanwal Jit Singh, Hillsboro, OR (US);

Tejaswi K Indukuri, Hillsboro, OR (US);

James S Clarke, Portland, OR (US);

Florian Gstrein, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Forefront IP Lawgroup, PLLC

Primary Examiner:

Jarrett Stark

Assistant Examiner:

Bitew Dinke

Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/76808 (2013.01); H01L 21/76843 (2013.01); H01L 21/76847 (2013.01); H01L 21/76849 (2013.01); H01L 21/76883 (2013.01); H01L 21/76886 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.

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Jezewski, Christopher. (2017). Forming barrier walls, capping, or alloys /compounds within metal lines (U.S. Patent No. 9659869). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9659869

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