The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2017
Filed:
Oct. 22, 2004
Bhadri Varadarajan, Beaverton, OR (US);
Sean Chang, Sunnyvale, CA (US);
James S. Sims, Tigard, OR (US);
Guangquan LU, Fremont, CA (US);
David Mordo, Cupertino, CA (US);
Kevin Ilcisin, Beaverton, OR (US);
Mandar Pandit, Wilsonville, OR (US);
Michael Carris, Tigard, OR (US);
Bhadri Varadarajan, Beaverton, OR (US);
Sean Chang, Sunnyvale, CA (US);
James S. Sims, Tigard, OR (US);
Guangquan Lu, Fremont, CA (US);
David Mordo, Cupertino, CA (US);
Kevin Ilcisin, Beaverton, OR (US);
Mandar Pandit, Wilsonville, OR (US);
Michael Carris, Tigard, OR (US);
Novellus Systems, Inc., Fremont, CA (US);
Abstract
A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. UV curing of as-deposited PECVD silicon nitride films, for example, has been shown to produce films with stresses of at least 1.65 E10 dynes/cm. Other dielectric capping layer film materials show similar results. In transistor implementations, the stress from a source/drain region capping layer composed of such a film is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel.