The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Dec. 16, 2015
Applicant:

Ibiden Co., Ltd., Ogaki-shi, JP;

Inventors:

Yasushi Inagaki, Ogaki, JP;

Toshiki Furutani, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/113 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H05K 1/111 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/18161 (2013.01); H05K 3/4682 (2013.01); H05K 2201/10674 (2013.01); Y02P 70/611 (2015.11);
Abstract

A printed wiring board includes a first insulating layer having concave portions on first surface of the first insulating layer, a first conductor layer including first circuits formed in the concave portions, a second conductor layer including second circuits on second surface of the first insulating layer, a first via conductor connecting the first and second conductor layers, and a second insulating layer formed on the second surface of the first insulating layer and covering the second conductor layer. Each first circuit has upper, lower and side surfaces such that the upper surface is exposed from the first insulating layer and the side and lower surfaces are not roughened surfaces, each second circuit has top, back and side surfaces such that the side and back surfaces are roughened surfaces, and a thinnest first circuit has a line width Lsmaller than a line width Lof a thinnest second circuit.


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