The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9653573 B1

PDF
Full Text
Expired
Date of Patent:
May. 16, 2017

Filed:

Aug. 17, 2015
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Linus Jang, Clifton Park, NY (US);

Sivananda K. Kanakasabapathy, Niskayuna, NY (US);

Sanjay C. Mehta, Niskayuna, NY (US);

Soon-Cheon Seo, Glenmont, NY (US);

Raghavasimhan Sreenivasan, Schenectady, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/283 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/283 (2013.01); H01L 21/3065 (2013.01); H01L 21/31144 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.


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