The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Sep. 25, 2015
Applicant:

Nepes Co., Ltd., Chungcheongbuk-do, KR;

Inventors:

Yong-Tae Kwon, Chungcheongbuk-do, KR;

Jun-Kyu Lee, Chungcheongbuk-do, KR;

Assignee:

NEPES CO., LTD., Chungcheongbuk-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/486 (2013.01); H01L 21/76829 (2013.01); H01L 23/49827 (2013.01); H01L 23/522 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/568 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/24227 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.


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