The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2017
Filed:
Jan. 07, 2016
United Microelectronics Corp., Hsin-Chu, TW;
Shang-Nan Chou, Tainan, TW;
Che-Yi Lin, Kaohsiung, TW;
En-Chiuan Liou, Tainan, TW;
Yu-Ting Hung, Hsinchu, TW;
Shin-Feng Su, Tainan, TW;
Chia-Hsun Tseng, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.