The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2017
Filed:
Oct. 02, 2014
Edward O. Travis, Austin, TX (US);
Ertugrul Demircan, Eugene, OR (US);
Douglas M. Reber, Austin, TX (US);
Michael A. Stockinger, Austin, TX (US);
Edward O. Travis, Austin, TX (US);
Ertugrul Demircan, Eugene, OR (US);
Douglas M. Reber, Austin, TX (US);
Michael A. Stockinger, Austin, TX (US);
NXP USA, Inc., Austin, TX (US);
Abstract
This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are 'pre-marked' and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.