The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Oct. 26, 2016
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Bejing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Qiang Zhang, Shanghai, CN;

Bin Xing, Shanghai, CN;

Jing An Hao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/68 (2006.01); H01L 21/768 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 21/687 (2006.01); H01L 21/67 (2006.01); H01L 21/027 (2006.01); G03F 9/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68 (2013.01); G03F 9/7015 (2013.01); H01L 21/027 (2013.01); H01L 21/67259 (2013.01); H01L 21/68714 (2013.01); H01L 21/76834 (2013.01); H01L 21/76892 (2013.01); H01L 22/20 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01);
Abstract

In some embodiments, an interconnection structure, an exposure alignment system, and a fabricating method thereof are provided. The method comprises: providing a wafer, forming a first to-be-connected member and multiple first alignment members in a first conductive layer; form a first opening and multiple second alignment members in a first mask layer, the first opening is used to define a position of a second to-be-connected member; based on reference and measurement coordinates of the first alignment members, and reference coordinates and measurement coordinates of the second alignment members, obtaining wafer coordinates for characterizing a position deviation of the wafer; obtaining adjustment compensation values according to stacking offsets of a preceding wafer; adjusting a position of the wafer; forming the interconnection structure in a first dielectric layer and a second dielectric layer to electrically interconnect the first to-be-connected member and the second to-be-connected member.


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