The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jun. 26, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ming-En Bu, Shanghai, CN;

Xiuli Yang, Shanghai, CN;

He-Zhou Wan, Shanghai, CN;

Mu-Jen Huang, Taipei, TW;

Jie Cai, Shanghai, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 8/16 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 8/16 (2013.01); G11C 7/1075 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01);
Abstract

In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.


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