The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2017
Filed:
Mar. 27, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Ruibing Lu, Santa Clara, CA (US);
Zhiyong Wang, Cupertino, CA (US);
Aaron Ng, Santa Clara, CA (US);
Sabyasachi Das, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); G06F 2217/84 (2013.01);
Abstract
Post-routing processing of a circuit design may include determining, using a processor, a baseline delay for a path of a routed circuit design, comparing, using the processor, the baseline delay of the path with a timing constraint of the path, and selectively applying, according to the comparing, a structural netlist optimization to the path resulting in an optimized path using a processor.
Lu, Ruibing. (2017). Post-routing structural netlist optimization for circuit designs (U.S. Patent No. 9646126). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9646126
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile