The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Mar. 19, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Alexei Sadovnikov, Sunnyvale, CA (US);

Jeffrey A. Babcock, Santa Clara, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/732 (2006.01); H01L 27/082 (2006.01); H01L 29/00 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 27/1203 (2013.01); H01L 29/0821 (2013.01); H01L 29/10 (2013.01); H01L 29/66265 (2013.01); H01L 29/66272 (2013.01); H01L 29/732 (2013.01); H01L 27/082 (2013.01); H01L 29/0649 (2013.01);
Abstract

Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.


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