The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Feb. 02, 2016
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Dengliang Yang, Union City, CA (US);

Joon Hong Park, Dublin, CA (US);

Assignee:

LAM RESEARCH CORPORATION, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3088 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H01L 21/3086 (2013.01);
Abstract

A method for processing a semiconductor substrate includes a) providing a substrate stack including a first layer, a plurality of cores arranged in a spaced relationship on the first layer and one or more underlying layers arranged below the first layer; b) depositing a conformal layer on the first layer and the plurality of cores; c) partially etching the conformal layer to create spacers arranged adjacent to sidewalls of the plurality of cores, wherein the partial etching of the conformal layer causes upper portions of the spacers to have an asymmetric profile; d) selectively etching the plurality of cores relative to the spacers and the first layer; e) depositing polymer film on sidewalls of the spacers; and f) etching the upper portions of the spacers to remove the asymmetric profile and to planarize the upper portions of the spacers.


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