The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

May. 22, 2015
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Te-Hsun Hsu, Hsinchu County, TW;

Chun-Hsiao Li, Hsinchu County, TW;

Hsuen-Wei Chen, Hsinchu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); G11C 16/08 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 27/112 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 17/04 (2006.01); G11C 17/08 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 29/93 (2006.01); H01L 27/11524 (2017.01); H03K 3/356 (2006.01); G11C 17/14 (2006.01); G11C 29/00 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 17/04 (2013.01); G11C 17/08 (2013.01); G11C 17/146 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/76 (2013.01); H01L 23/528 (2013.01); H01L 27/0629 (2013.01); H01L 27/11206 (2013.01); H01L 27/11524 (2013.01); H01L 29/1079 (2013.01); H01L 29/4916 (2013.01); H01L 29/93 (2013.01); H03K 3/356182 (2013.01); H01L 23/5252 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.


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