The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Jun. 03, 2015
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Wei-Ren Chen, Pingtung County, TW;

Wen-Hao Lee, Hsinchu County, TW;

Hsin-Chou Liu, Kaohsiung, TW;

Ching-Sung Yang, Hsinchu, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/08 (2006.01); H01L 31/02 (2006.01); G01D 5/24 (2006.01); H01L 27/115 (2017.01); H01L 27/02 (2006.01); H01L 23/552 (2006.01); H01L 27/112 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G06K 9/00 (2006.01);
U.S. Cl.
CPC ...
G01D 5/24 (2013.01); G06K 9/0002 (2013.01); G11C 29/1201 (2013.01); G11C 29/78 (2013.01); H01L 23/552 (2013.01); H01L 27/0248 (2013.01); H01L 27/115 (2013.01); H01L 27/11206 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated capacitance sensing module includes a silicon substrate, a first and a second and a third interlayer dielectric layers, plural conducting layers, a shielding layer, a lower and a upper sensing electrode layers, a protective coating layer. An embedded memory and a sensing circuit are constructed in the silicon substrate. The first interlayer dielectric layer covers the silicon substrate. The plural conducting layers are formed over the first interlayer dielectric layer. The shielding layer is formed over the plural conducting layers. The second interlayer dielectric layer covers the shielding layer. The lower sensing electrode layer is formed over the second interlayer dielectric layer. The third interlayer dielectric layer is formed over the lower sensing electrode layer. The upper sensing electrode layer is formed over the third interlayer dielectric layer. The protective coating layer covers the upper sensing electrode layer.


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