The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Aug. 01, 2016
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Chien Sheng Su, Saratoga, CA (US);

Mandana Tadayoni, Cupertino, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/762 (2006.01); H01L 27/11521 (2017.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/11534 (2017.01); H01L 27/11531 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/02532 (2013.01); H01L 21/02634 (2013.01); H01L 21/28035 (2013.01); H01L 21/28273 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/11531 (2013.01); H01L 27/11534 (2013.01); H01L 29/0847 (2013.01); H01L 29/42328 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01);
Abstract

A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate.


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