The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Jan. 06, 2016
Applicants:

Global Unichip Corporation, Hsinchu, TW;

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yen-Chung Chen, Santa Clara, CA (US);

Tsai-Ming Yang, Hsinchu, TW;

Yi-Lin Lee, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356017 (2013.01); H03K 3/012 (2013.01);
Abstract

A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.


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