The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 18, 2017

Filed:

Nov. 24, 2014
Applicant:

Adesto Technologies Corporation, Sunnyvale, CA (US);

Inventor:

Michael A. Van Buskirk, Saratoga, CA (US);

Assignee:

ADESTO TECHNOLOGIES CORPORATION, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); H01L 27/0629 (2013.01); H01L 29/7841 (2013.01); H01L 29/861 (2013.01); G11C 2213/78 (2013.01); G11C 2213/79 (2013.01);
Abstract

In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.


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