The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
May. 08, 2014
Applicants:
Soitec, Bernin, FR;
Stmicroelectronics, Inc., Coppell, TX (US);
Inventors:
Frédéric Allibert, Albany, NY (US);
Pierre Morin, Albany, NY (US);
Assignees:
SOITEC, Bernin, FR;
STMICROELECTRONICS, INC., Coppell, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/205 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02532 (2013.01); H01L 21/02614 (2013.01); H01L 21/02694 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 29/205 (2013.01);
Abstract
Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.