The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Dec. 18, 2015
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Seng Guan Chow, Singapore, SG;

Lee Sun Lim, Singapore, SG;

Rui Huang, Singapore, SG;

Xu Sheng Bao, Singapore, SG;

Ma Phoo Pwint Hlaing, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/146 (2006.01); B81C 1/00 (2006.01); H01L 25/16 (2006.01); H01L 31/0203 (2014.01);
U.S. Cl.
CPC ...
H01L 27/1469 (2013.01); B81C 1/0023 (2013.01); H01L 21/76898 (2013.01); H01L 25/165 (2013.01); H01L 25/167 (2013.01); H01L 27/14618 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 31/0203 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.


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