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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9620445 B1

PDFFull Text
Date of Patent:
Apr. 11, 2017

Filed:

Apr. 06, 2016

Chip package structure and method of manufacturing the same

Applicant:

Chipmos Technologies Inc., Hsinchu, TW;

Inventors:

Tung-Bao Lu, Hsinchu, TW;

Tzu-Han Hsu, Hsinchu, TW;

Assignee:

ChipMOS Technologies Inc., Hsinchu, TW;

Attorney:

Jianq Chyun IP Office

Primary Examiner:

Hsien Ming Lee

Int. Cl.
CPC ...
H01L 23/06 (2006.01); H01L 23/48 (2006.01); H01L 23/34 (2006.01); H01L 21/8222 (2006.01); H01L 21/20 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/48 (2013.01); H01L 21/4853 (2013.01); H01L 23/49805 (2013.01); H01L 23/64 (2013.01);
Abstract

A chip package structure including a chip, a circuit layer, a passive element material and a substrate is provided. The circuit layer is disposed on a surface of the chip, wherein the circuit layer includes a plurality of bumps and a plurality of passive element electrodes. The bumps and the passive element electrodes have the same material, and the passive element electrodes are electrically connected with part of the bumps. The passive element material is disposed between the passive element electrodes, so that the passive element electrodes and the passive element material form a passive element located on the surface of the chip. The chip is disposed on the substrate and faces the substrate by the surface, so that the chip and the passive element are electrically connected to the substrate through the bumps. A method of manufacturing the chip package structure aforementioned is also provided.

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