The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Nov. 12, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd.;

Inventors:

Liang Li, Singapore, SG;

Wei Lu, Singapore, SG;

Lian Choo Goh, Singapore, SG;

Yung Fu Alfred Chong, Singapore, SG;

Fangyue Liu, Singapore, SG;

Alex See, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823462 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01);
Abstract

Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.


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