The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2017
Filed:
Aug. 05, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Ming-Chyi Liu, Hsin-Chu, TW;
Wei-Hang Huang, Kaohsiung, TW;
Yu-Hsing Chang, Taipei, TW;
Chang-Ming Wu, New Taipei, TW;
Wei Cheng Wu, Zhubei, TW;
Shih-Chang Liu, Alian Township, TW;
Harry-Hak-Lay Chuang, Singapore, SG;
Chia-Shiung Tsai, Hsin-Chu, TW;
Ru-Liang Lee, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.