The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Mar. 09, 2016
Applicant:

Winbond Electronics Corporation, Taichung, TW;

Inventors:

Robin John Jigour, San Jose, CA (US);

Hui Chen, San Ramon, CA (US);

Oron Michael, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 29/04 (2006.01); G06F 11/10 (2006.01); G11C 16/34 (2006.01); G11C 16/20 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 11/1068 (2013.01); G11C 16/3404 (2013.01); G11C 29/04 (2013.01); G11C 16/20 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR ('HPSF-NOR') memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND ('SPSF-NAND') memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.


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