The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Apr. 04, 2014
Applicants:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
National Taiwan University, Taipei, TW;
Inventors:
Ming-Han Liao, Taipei, TW;
Minghwei Hong, Zhubei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/82 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); C23C 14/16 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); C23C 14/165 (2013.01); H01L 29/165 (2013.01); H01L 29/401 (2013.01); H01L 29/4966 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01); H01L 21/28194 (2013.01);
Abstract
An integrated circuit structure includes a semiconductor substrate, and a gate stack over the semiconductor substrate. The gate stack includes a high-k gate dielectric over the semiconductor substrate, and a magnetic compound over and in contact with the high-k gate dielectric. A source region and a drain region are on opposite sides of the gate stack. The gate stack, the source region, and the drain region are portions of a Metal-Oxide-Semiconductor (MOS) device.