The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Feb. 19, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Yang Pai, Hsinchu, TW;

Kuo-Chi Tu, Hsinchu, TW;

Wen-Chuan Chiang, Hsinchu, TW;

Chung-Yen Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); H01L 21/76832 (2013.01); H01L 21/76879 (2013.01); H01L 21/76897 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 27/108 (2013.01); H01L 27/1085 (2013.01); H01L 27/10855 (2013.01); H01L 27/10894 (2013.01); H01L 28/40 (2013.01); H01L 28/90 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first opening in the first etch stop layer and the first dielectric layer. The method further comprises filling the first opening with a conductive material. The method additionally comprises forming a second etch stop layer and a second dielectric layer over the first etch stop layer. The method further comprises forming a second opening to expose the conductive material. The method additionally comprises forming a capacitor in the second opening and in contact with the conductive material.


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