The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 04, 2017

Filed:

Dec. 31, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eng Huat Goh, Ayer Itam, MY;

Hoay Tien Teoh, Paya Terubong, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/50 (2006.01); H01L 23/48 (2006.01); H01L 23/29 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 21/50 (2013.01); H01L 21/76898 (2013.01); H01L 23/295 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/25 (2013.01); H01L 24/13 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/2518 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.


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