The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2017
Filed:
Dec. 18, 2015
Applied Materials, Inc., Santa Clara, CA (US);
Annamalai Lakshmanan, Fremont, CA (US);
Bencherki Mebarki, Santa Clara, CA (US);
Kaushal K. Singh, Santa Clara, CA (US);
Paul F. Ma, Santa Clara, CA (US);
Mehul B. Naik, San Jose, CA (US);
Andrew Cockburn, Brussels, BE;
Ludovic Godet, Sunnyvale, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.