The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Mar. 13, 2014
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventors:

Eung San Cho, Torrance, CA (US);

Chuan Cheah, Torrance, CA (US);

Andrew N. Sawle, East Grinstead, GB;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 25/07 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 24/36 (2013.01); H01L 24/37 (2013.01); H01L 24/40 (2013.01); H01L 25/074 (2013.01); H01L 23/3107 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/37147 (2013.01); H01L 2224/40095 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/73221 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/181 (2013.01); H01L 2924/30107 (2013.01);
Abstract

According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.


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