The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Oct. 17, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Yao Wen, Hsin-Chu, TW;

Sai-Hooi Yeong, Zhubei, TW;

Sheng-Chen Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823412 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01);
Abstract

A FinFET and methods for forming a FinFET are disclosed. In a method, first trenches are formed in a substrate. First isolation regions are then formed in the first trenches. An epitaxial region is epitaxially grown between the first isolation regions. A second trench is formed by etching in the epitaxial region, forming a plurality of fins. A second isolation region is formed in the second trench. A structure includes a substrate, a first fin on the substrate, a gate dielectric over the first fin, and a gate electrode over the gate dielectric. The first fin comprises an epitaxial layer having a stacking fault defect density less than 1*10cm.


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