The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Mar. 22, 2012
Applicants:

Yujuan Tao, Nantong, CN;

Lei Shi, Nantong, CN;

Inventors:

Yujuan Tao, Nantong, CN;

Lei Shi, Nantong, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/50 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19105 (2013.01);
Abstract

A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate.


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Tao, Yujuan. (2017). 3d system-level packaging methods and structures (U.S. Patent No. 9595490). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9595490

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