The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2017

Filed:

Nov. 05, 2012
Applicants:

Henning F. Spruth, Austin, TX (US);

Qadeer A. Qureshi, Dripping Springs, TX (US);

Reinaldo Silveira, Sao Paulo, BR;

Inventors:

Henning F. Spruth, Austin, TX (US);

Qadeer A. Qureshi, Dripping Springs, TX (US);

Reinaldo Silveira, Sao Paulo, BR;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 7/20 (2006.01); G11C 7/24 (2006.01); G01R 31/3181 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12 (2013.01); G11C 7/20 (2013.01); G11C 7/24 (2013.01); G01R 31/3181 (2013.01); G01R 31/3187 (2013.01);
Abstract

Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.


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