The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Aug. 25, 2014
Applicant:

Csmc Technologies Fab1 Co., Ltd., Wuxi New District, CN;

Inventors:

Shengrong Zhong, Wuxi New District, CN;

Dongfei Zhou, Wuxi New District, CN;

Xiaoshe Deng, Wuxi New District, CN;

Genyi Wang, Wuxi New District, CN;

Assignee:

CSMC Technologies Fab1 Co., Ltd., Wuxi New District, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/161 (2006.01); H01L 29/04 (2006.01); H01L 21/761 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0623 (2013.01); H01L 21/761 (2013.01); H01L 29/045 (2013.01); H01L 29/1095 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/1608 (2013.01); H01L 29/20 (2013.01); H01L 29/401 (2013.01); H01L 29/407 (2013.01); H01L 29/408 (2013.01); H01L 29/66333 (2013.01); H01L 29/7395 (2013.01);
Abstract

A method for manufacturing an insulated gate bipolar transistor () comprises: providing a substrate (), forming a field oxide layer () on a front surface of the substrate (), and forming a terminal protection ring (); performing photoetching and etching on the active region field oxide layer () by using an active region photomask, introducing N-type ions into the substrate () by using a photoresist as a mask film; depositing and forming a polysilicon gate () on the etched substrate () of the field oxide layer (), and forming a protection layer on the polysilicon gate (); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.


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