The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Mar. 31, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Daniel Edelstein, White Plains, NY (US);

Takeshi Nogami, Schenectady, NY (US);

Christopher Parks, Poughkeepsie, NY (US);

Tsong Lin Leo Tai, Stormville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/76849 (2013.01); H01L 21/76867 (2013.01); H01L 21/76883 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 23/522 (2013.01); H01L 23/53209 (2013.01); H01L 24/76 (2013.01); H01L 24/82 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.


Find Patent Forward Citations

Loading…