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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9589885 B1

PDFFull Text
Expired
Date of Patent:
Mar. 07, 2017

Filed:

Aug. 26, 2015

Device having multiple-layer pins in memory mux1 layout

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Jen Liao, Hsinchu, TW;

Jung-Hsuan Chen, Hsinchu, TW;

Chien Chi Tien, Hsinchu, TW;

Ching-Wei Wu, Caotun Town, TW;

Jui-Che Tsai, Tainan, TW;

Hong-Chen Cheng, Hsinchu, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., , TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Ngan Ngo

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 27/11 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/50 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53204 (2013.01); H01L 27/0203 (2013.01); H01L 27/11 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Find Patent Forward Citations

Liao, Hung-Jen. (2017). Device having multiple-layer pins in memory mux1 layout (U.S. Patent No. 9589885). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9589885

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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