The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2017

Filed:

Dec. 16, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsinchu, TW;

Inventors:

Kuo-Yu Cheng, Tainan, TW;

Keng-Yu Chen, Tainan, TW;

Wei-Kung Tsai, Tainan, TW;

Kuan-Chi Tsai, Kaohsiung, TW;

Tsung-Yu Yang, Zhubei, TW;

Chung-Long Chang, Hsinchu, TW;

Chun-Hung Chen, Xinpu Township, TW;

Chih-Ping Chao, Juhdong Town, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H01L 21/7624 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01);
Abstract

A method for forming a radio frequency area of an integrated circuit are provided. The method includes forming a buried oxide layer over a substrate, and an interface layer is formed between the substrate and the buried oxide layer. The method also includes etching through the buried oxide layer and the interface layer to form a deep trench, and a bottom surface of the deep trench is level with a bottom surface of the interface layer. The method further includes forming an implant region directly below the deep trench and forming an interlayer dielectric layer in the deep trench.


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