The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Oct. 08, 2015
Method of converting between non-volatile memory technologies and system for implementing the method
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5068 (2013.01); G06F 17/5077 (2013.01); H01L 27/0207 (2013.01); H01L 27/11573 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); G06F 2217/06 (2013.01); G06F 2217/78 (2013.01); H01L 27/11531 (2013.01);
Abstract
A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors.