The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2017
Filed:
Dec. 19, 2014
Industrial Technology Research Institute, Hsinchu, TW;
Chih-Yen Lo, Hsinchu, TW;
Ding-Ming Kwai, Zhubei, TW;
Chi-Chun Yang, Taichung, TW;
Kuan-Te Wu, New Taipei, TW;
Yun-Chao Yu, Taipei, TW;
Jin-Fu Li, Pingzhen, TW;
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Hsinchu, TW;
Abstract
A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, μ data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<μ<M.