The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Sep. 02, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Giovanni Calabrese, Munich, DE;

Domagoj Siprak, Munich, DE;

Wolfgang Molzer, Ottobrunn, DE;

Uwe Hodel, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/223 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66681 (2013.01); H01L 21/02057 (2013.01); H01L 21/2236 (2013.01); H01L 21/26506 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 21/76237 (2013.01); H01L 29/0619 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01);
Abstract

Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.


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