Method for manufacturing injection-enhanced insulated-gate bipolar transistor

Abstract

A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate () is provided; a p-type doped layer () is formed on the n-type substrate (); a hard layer () is formed on the p-type doped layer (); a groove () extending to the n-type substrate () is formed by etching on the p-type doped layer (); an n-type doped layer () is formed on the sidewalls and bottom of the groove (); the hard layer () is removed; p-type impurities of the p-type doped layer () and n-type impurities of the n-type doped layer () are driven in together, where the p-type impurities are diffused to form a p-type base region (), and the n-type impurities are diffused to form an n-type buffer layer (); a gated oxide dielectric layer () is formed on the surface of the groove (); and, a polysilicon layer () is deposited in the groove having formed therein the gate oxide dielectric layer (). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer () and the n-type doped layer () are driven in together to form the p-type base region () and the n-type buffer layer (), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.