The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 28, 2017

Filed:

Jun. 30, 2015
Applicant:

Towa Corporation, Kyoto-shi, Kyoto, JP;

Inventors:

Hirokazu Okada, Kyoto, JP;

Hiroshi Uragami, Kyoto, JP;

Tsuyoshi Amakawa, Kyoto, JP;

Muneo Miura, Kyoto, JP;

Assignee:

Towa Corporation, Kyoto-shi, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); C25D 1/00 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H01L 21/56 (2006.01); H05K 3/28 (2006.01);
U.S. Cl.
CPC ...
C25D 1/00 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/552 (2013.01); H01L 24/97 (2013.01); H05K 1/0209 (2013.01); H05K 1/0216 (2013.01); H01L 2924/14 (2013.01); H05K 3/284 (2013.01); H05K 2201/066 (2013.01); H05K 2201/10371 (2013.01);
Abstract

The present invention provides a method for producing an electronic component, capable of simply and efficiently producing an electronic component having both of a via electrode(s) (bump(s)) and a plate-like member. The method is a method for producing an electronic component. The electronic component includes: a substrate, a chip(s), a resin, a plate-like memberhaving a surface(s), a bump(s)that includes a deformable portionA, and a wiring pattern. The method includes: disposing the chip(s)on the surface(s); and encapsulating the bump(s)in the resin. The encapsulating includes: encapsulating the chip(s)in the resinbetween a bump-formed surface of the plate-like memberon which the bump(s)is formed and a wiring pattern-formed surface of the substrateon which the wiring pattern is formed; and causing the bump(s)to be in contact with the wiring pattern


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