The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Aug. 10, 2015
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Shih-Liang Cheng, Taipei, TW;

Dyi-Chung Hu, Hsinchu County, TW;

Yu-Hua Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 1/02 (2006.01); H05K 3/40 (2006.01); H05K 1/09 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/11 (2013.01); H05K 1/0274 (2013.01); H05K 1/0298 (2013.01); H05K 1/09 (2013.01); H05K 1/182 (2013.01); H05K 3/007 (2013.01); H05K 3/0017 (2013.01); H05K 3/0097 (2013.01); H05K 3/4038 (2013.01);
Abstract

A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.


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