The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Nov. 07, 2010
Applicants:
Zvi Or-bach, San Jose, CA (US);
Ze'ev Wurman, Palo Alto, CA (US);
Inventors:
Zvi Or-Bach, San Jose, CA (US);
Ze'ev Wurman, Palo Alto, CA (US);
Assignee:
MONOLITHIC 3D INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17748 (2013.01); H03K 19/1778 (2013.01); H03K 19/17736 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.