The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Sep. 14, 2015
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 47/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/124 (2013.01); H01L 27/2409 (2013.01); H01L 27/2445 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 29/02 (2013.01); H01L 45/06 (2013.01); H01L 45/065 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/144 (2013.01); H01L 45/16 (2013.01); H01L 45/1691 (2013.01);
Abstract
Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.