The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Apr. 24, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shih-Chieh Pu, New Taipei, TW;

Ping-Hung Chiang, Hsinchu, TW;

Chang-Po Hsiung, Hsinchu, TW;

Chia-Lin Wang, Yunlin County, TW;

Nien-Chung Li, Hsinchu, TW;

Wen-Fang Lee, Hsinchu, TW;

Shih-Yin Hsiao, Chiayi County, TW;

Chih-Chung Wang, Hsinchu, TW;

Kuan-Lin Liu, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/308 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66568 (2013.01); H01L 21/02238 (2013.01); H01L 21/28167 (2013.01); H01L 21/3081 (2013.01); H01L 29/0649 (2013.01); H01L 29/66681 (2013.01);
Abstract

A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.


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